This invention is in the field of flash memory systems, and is more specifically directed to the initialization of flash memory as used for integrated digital systems.
The popularity of the non-volatile solid-state memory technology that is commonly referred to as “flash” memory has greatly increased in recent years. Flash memory typically refers to electrically-erasable semiconductor memory that can be erased and rewritten in relatively small blocks, rather than on a chip-wide basis, or in relatively large blocks as in conventional EEPROM devices. Flash memory has become especially popular for applications in which non-volatility (i.e., data retention after removal of power) of the stored data is essential, but in which the frequency of rewriting is relatively low. Examples of popular applications of flash memory include portable audio players, “SIM” card storage of telephone numbers and phone activity in cellular telephone handsets, “thumbkey” removable storage devices for computers and workstations, storage devices for digital cameras, and the like.
Typical conventional flash memory products are effectively arranged as “chipsets” consisting of one or more integrated circuits that include the flash memory storage resource in the form of one or more devices (or “arrays”), and an integrated circuit that serves as the memory controller for the flash memory product. The flash memory array may be arranged as so-called NOR flash memory, in which individual memory cells may be randomly accessed, or so-called NAND flash memory, in which sequential access of a page or block of memory is necessitated. As known in the art, each of these flash memory arrangements has advantages and disadvantages. For example, NOR flash memory is especially advantageous for small capacity code storage, while NAND flash memory is especially useful for high capacity data storage such as for audio players and digital cameras. In recent years, the use of multi-level cell (MLC) flash memory, in which each flash memory cell can store a multi-bit data value (typically a two bit value, stored as one of four possible states), has become popular, especially in NAND flash memory.
According to one typical arrangement, flash memory is manufactured and sold as a flash memory subsystem containing the flash memory resources and the subsystem controller mounted onto a card. Examples of such subsystems included the well-known COMPACT FLASH (CF) cards, Secure Digital (SD) cards, and MULTIMEDIA cards. FIG. 1 illustrates an exemplary conventional flash memory system 2, in block diagram form. In this arrangement, multiple flash memory devices (“arrays”) 12 are connected to subsystem controller 10 by way of flash media interface FMI, which is typically a bus that communicates physical address signals and control signals from subsystem controller 10, and that bidirectionally communicates data to and from devices 12. Subsystem controller 10 is connected by way of interface bus IF to connector C. As is well known in the art, flash memory system 2 can be inserted into or otherwise connected to a host device, such as a camera, computer, audio player, and the like by way of connector C. Connector C and interface bus IF are arranged according to the particular standard according to which flash memory system 2 is constructed and realized (e.g., as a CF card, an SD card, or a MULTIMEDIA card).
In other known arrangements (e.g., SMART MEDIA cards), the flash memory systems do not include a subsystem controller. In such arrangements, referring to FIG. 1 by way of analogy, flash media interface FMI connects to a controller located externally from the flash memory system, for example a controller that is included in the host device (e.g., camera) utilizing the flash memory.
Typically, conventional flash memory arrays are not formatted or initialized (beyond, perhaps, the marking of defective blocks established at the chip test level) until after their assembly into a card. Flash memory initialization typically includes such functions as formatting the arrays according to a file system, generating defect maps so that physically defective memory locations are avoided in use, low-level user area formatting of the memory arrays, loading a disk image of application software that may be executed by a system using the flash memory system and, for those systems in which the subsystem controller is implemented, downloading firmware and operating parameters, trimming local oscillator frequencies, and the like. The result of the initialization process is a flash memory system in which data can be written and read at physical locations corresponding to a logical address from the host system. In addition, it is contemplated that the configuration of the flash memory system can also be updated during operation, should a portion of the physical memory become defective, or if additional disk image data is to be stored for add-on applications.
Generally, the initialization of flash memory resources is typically performed by the flash memory system manufacturer, typically after flash memory devices 12 and subsystem controller 10 are mounted to the ultimate system board and thus interconnected, in the conventional manner. As shown in FIG. 2, by way of example, after its manufacture, flash memory system 2 is connected to tester TSTR via connector C and a test cable DUT_CBL. Tester TSTR will communicate with flash memory system 2 over test cable DUT_CBL and connector C, to ensure continuity of the electrical connections in flash memory system 2, to ensure proper DC behavior of the terminals of connector C, and to perform certain rudimentary functional tests as can be executed prior to initialization of flash memory devices 12. In addition, as known in the art, tester TSTR typically can apply diagnostic commands to flash memory system 2, specifically to controller 10, for testing the functionality of flash memory system 2 including its flash memory devices 12, and for initializing flash memory system 2. As mentioned above, conventional initialization of flash memory system 2 includes formatting and configuring the flash memory resources of flash memory devices 12, detecting and logging physically defective memory locations of flash memory devices 12, loading a control program (“firmware”) into controller 10 (e.g., into NOR flash memory embedded within controller 10), and loading application software, in the form of DOS or disk images into flash memory devices 12, as suitable for use in the intended application. Examples of such application software include data encryption software, wear leveling algorithms, and the like that can be executed by controller 10.
Recently, however, flash memory storage has become desirable for use in connection with many new applications, including those which are controlled by a so-called “system-on-a-chip”, or “SOC”. In these contemplated SOC applications, a single integrated circuit integrates the central processing unit (CPU), its system memory (RAM and ROM), standard interface functions (e.g., USB, serial I/O, etc.), and other peripherals useful in the system. As presently configured, an SOC architecture for a consumer device that uses flash memory, in order to take advantage of its non-volatile rewritable storage features, would also integrate the flash memory subsystem controller into the SOC, with an external interface from the SOC to the flash memory devices. FIG. 3 illustrates such a conventional arrangement of an SOC-based architecture using flash memory, as will now be described.
As shown in FIG. 3, SOC 20 interfaces with flash memory 35, typically arranged as one or more NAND flash memory devices (although, of course, NOR flash memory may instead be used) by way of conventional flash memory interface NAND_IF. In this arrangement, flash memory subsystem controller 29 is realized within SOC 20, rather than as part of a flash memory subsystem as described above in FIG. 1. SOC 20 is indeed a system-on-a-chip, and as such includes CPU 22 and various system functions such as system ROM 24, system RAM 26, and standard interfaces 30 (e.g., USB, SCSI, RS-232, or other interfaces) to which CPU 22 is connected by way of a conventional bus CPU_BUS as shown in FIG. 3. Other peripherals may also be included within SOC 20, and communicate with CPU 22 via bus bridge 28 and peripheral bus PER_BUS. One such peripheral, in the example of FIG. 3, is subsystem controller 29, which is coupled to peripheral bus PER_BUS by way of standard interfaces 27A, 27B that translate signals between peripheral bus PER_BUS and subsystem controller 29; this translation enable a conventional subsystem controller 29 to be readily implemented within SOC 29 without requiring wholesale redesign. As such, SOC 22 can readily operate in a manner that uses flash memory 35 as non-volatile storage, analogous to disk storage. For example, bulk data storage may be maintained on flash memory 35, as can application programs. For example, application programs stored on flash memory 35 can be loaded via subsystem controller 29 (and buses PER_BUS, CPU_BUS and the various interfaces and bridges) into system RAM 26 for execution by CPU 22, in much the same manner as an application program is called and loaded from disk storage in a larger system. Similarly, data can be stored and accessed by CPU 22 from flash memory 35 by way of subsystem controller 29.
Unfortunately, conventional initialization methodologies cannot readily initialize flash memory 35 in this configuration, in which subsystem controller 29 is separated from flash memory and is embodied within SOC 20. In particular, certain portions of flash memory 35 are not accessible except by way of a corresponding subsystem controller (such as subsystem controller 29), and it is these “system” portions of flash memory 35 that are involved in the initialization process. Prior to initialization, however, in the conventional SOC arrangement of FIG. 3, subsystem controller 29 is not accessible for initialization of flash memory 35. FIG. 3 illustrates a brute force approach, as conjectured in connection with this invention, to the initialization of flash memory 35 in an SOC configuration, by way of which tester TSTR connects to a specially designed interface of flash memory 35, via special bus SPC_BUS, and executes diagnostic commands via this interface to effect initialization. However, this conjectured approach requires the creation of special test hardware (tester TSTR and special bus SPC_BUS), as well as creation of the special interface into flash memory 35, both of which would add substantial cost to the manufacture and production of the system, and would limit the flexibility with which the system may be configured and initialized.
By way of further background, U.S. Pat. No. 6,009,496 describes a microcontroller architecture with embedded flash memory, in which an on-board microprocessor executes a reprogramming control routine, stored in on-board read-only memory, to reprogram the embedded flash memory. This U.S. Pat. No. 6,009,496 also discloses that the microcontroller system can be manually set into this reprogramming mode when newly fabricated, in which case the microprocessor executes the reprogramming control routine from the on-board ROM to program the embedded flash memory with data received over an external interface.